The ever-growing ultra-thin and ultra-light weight portable mobile devices market has driven the great demand for system-on-a-chip (SoC) designs that come along with tens to hundreds of systems or sub-systems being integrated onto a single chip. The scaling of physical dimensions of most recent portable mobile devices has put a bottleneck on the power supply capability provided by the battery. To prolong the lifetime of these portable devices which contain high-performance SoC with high power consumption, the supply voltage of most of the digital integrated circuits (IC) has to scale down to sub-threshold or near-threshold region, especially during standby or idling mode. However, conventional power management techniques implemented mostly in analog circuits cannot provide the required performance, given that analog circuits with scaling supply voltage have to consume more power to maintain performance, such as high gain and high bandwidth.
It has since been a challenge in power management IC (PMIC) design to achieve generation of a fine regulated supply voltage with ultra-fast transient responses that can deliver current ranging from hundreds of milli-amperes to several amperes for digital circuits in the SoC. Digital linear voltage regulators, or sometimes referred to as digital low dropout regulators, is a new category of PMIC that has the potential to fit in these stringent power management requirements of SoC. Digital linear voltage regulators distinguish themselves from their analog counterparts mainly by using a digital controller loop to fully turn-on or turn-off for a portion of or whole units of pass transistors that act as power stages. Conventional digital linear regulator designs can provide functional but non-optimized performance, but these designs suffer from slow transient response or high quiescent current consumption, which are not preferred in PMIC design for a large system such as an SoC.